For numbers 2 and 3 can/should we apply multi-level minimization before
drawing the diagram? (particularly for number 2, not sure if it would be
possible/useful in number 3 yet)

Thanks,
Will

-- 
William T. O'Neill
Northwestern University '11
McCormick School of Engineering and Applied Science
On Mon, Nov 3, 2008 at 4:14 PM, James Swaine <
jamesswaine2010@u.northwestern.edu> wrote:
> also, for (3a) and (3b), do we need to draw the actual gate-level
> implementation of the mux and decoder or just the block with
> inputs/outputs/control lines?
>
> On Mon, Nov 3, 2008 at 11:48 AM, Mykell Miller <mykell.shih@gmail.com>wrote:
>
>> You can use an inverter if necessary.
>>
>>
>> On Mon, Nov 3, 2008 at 11:40 AM, James Swaine <
>> jamesswaine2010@u.northwestern.edu> wrote:
>>
>>> On questions (2A) and (2B), are we ONLY able to use the types of gates
>>> mentioned in our implementation of the function?  So for example, in (2A),
>>> our circuit is only allowed to contain NAND gates?  This seems to be implied
>>> by the wording of the question, but I just wanted to make sure.
>>>
>>> Thanks,
>>> James
>>>
>>
>>
>>
>> --
>> Mykell Miller
>>
>
>