EECS 303 Mailing List
Lab 3 - simulating with typ. delays

Lab 3 - simulating with typ. delays

From: Ben Schnur <b-schnur_at_avoiding.spam>
Date: Fri Nov 14 2008 - 17:52:43 EST

Hello all.

I'm having an issue when I get to the simulation stage:

Although I have set delays to Full Delays: typ, there are no delays
apparent in the traces.

The big problem with this is that I need the H signal to not go down
immediately on the clock edge where the state changes to a state where
H becomes 0.

It should wait briefly as the new state values pass through the
combinational logic, right?

If it doesn't delay at all and goes down on the edge, it might be read
as zero and the data would then only be driven for two cycles.

What is exasperating is that the state machine I entered reflects the
proper behavior of the machine, but the traces do not reflect this.

Do i need to do something else in addition to setting the delay to
full delays: typ?

(Even if I zoom in as far as I can, the transition appears to be
happening right on the edge.)


Ben Schnur
Received on Fri Nov 14 16:52:43 2008

This archive was generated by hypermail 2.1.8 : Tue Jan 06 2009 - 18:55:01 EST