EECS 303 Mailing List
Re: lab 4 unoptimized printout

Re: lab 4 unoptimized printout

From: Robert Dick <dickrp_at_avoiding.spam>
Date: Mon Dec 01 2008 - 22:34:30 EST

William O'Neill:
> Hello,
> I was wondering what people were doing for the printout of the unoptimized
> design. The text is literally unreadable because the design is so large.
> I'm assuming the purpose of this step is to appreciate the optimization
> process, so is it acceptable if the unoptimized design printout cannot be
> read?

If the text is too small to easily read, that is O.K. Although we will be
checking your VHDL carefully, we won't be mentally simulating the behavior
the synthesis software so we'll need to take your word that the output you
show corresponds to the VHDL code you hand in.

Mykell Miller:
) The unoptimized design still has to be gradable, so it must be readable. If
) gates are unreadable, take advantage of hierarchy to make it more readable.
) If text is unreadable, handwrite enough labels so I can figure out what's
) going on (~1/4 of the gates should be enough)

Mykell: If I understood him correctly, he is talking about the big gate-level
diagram that Design Compiler produces (not a hand-prepared design). For that
one, it is O.K. to trust that the diagram was the result of the VHDL, but it
is necessary to check the VHDL.

-Robert Dick-
Received on Mon Dec 1 21:34:30 2008

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