Help with common problems with CAD software

  1. Long load time
  2. Can't write file, can only read
  3. Warning about cold soldering wire
  4. Need to print black on white, how to invert color scheme
  5. MOSFET symbols.
  6. How to use “integ” function.

Problem: long load time (from Gianting Yeh, Zhi Lily Li, and David Bild)

If Cadence isn't loading up instantly, it may have something to do with your log files. This is usually due to you not closing the program properly and it just sort of tweaks out. To fix you can

  1. Delete the log file. Although if you click on the log file, it'll say “WARNING DO NOT EDIT” just ignore that cause if it isn't working already, then you can't break it anymore.
  2. You can use a -log type login if you are truly paranoid. This would be for instance at the terminal
    icfb -log /afs/[path to user dir]/desktop/tempLog/bad.log
    This command creates a log named bad.log. Pretty much a junk log. Do this if you are truly paranoid about messing up the log file before hand.

After you've closed the cadence software, it's ok to delete any of the *.log files it leaves lying around. These are for your benefit; if something isn't working properly you can analyze the log messages for help in diagnosing the root cause. But if your only trouble is opening ICFB in the first place, just delete the log files.

Problem: Can't write file, can only read (from Gianting Yeh and David Bild)

This problem is when you open up your saved schematic and it'll give you a warning message, saying something to the point, you can only read the file but not write to it. I only know of a few people that have this problem so hopefully this helps. This problem arises once again if you don't shut the program off properly. To fix this issue, you need to follow these steps.

  1. Locate wherever your schematic file is.
  2. Delete ANY file with the following type at the end *.cdslck. For instance, I had deleted a file named sch.cdb.cdslck. This file caused problems where it would lock the file.

The *.cdslck files are created to indicate that a certain file is in use (e.g., sch.cdb.cdslck indicates taht file sch.cdb is open for editing). Only the program which created the .cdslck file can edit the corresponding file. This ensures that two instances of the program can both try to make changes to the same file, totally hosing the file in the process. This would be quite useful, for instance, in large projects where multiple engineers are accessing the same set of schematics.

Of course, if you're positive that no one else is actually using the file (for instance, in the single-person labs) then of course you can just delete the occasional orphan lock.

Problem: Warning about cold soldering wire (from Gianting Yeh and David Bild)

This was mentioned earlier in one of the threads of some people having problems. To fix this, move the ground wire and connect it to wherever it's claiming there is a soldering problem. In other words, make sure all the wires connect directly to the ground node, and not all the wires coming to one node, and then THAT node connecting to the ground.

Note that this solution will work only for solder dots on a wire connected to ground. For the upcoming larger labs, you'll have nets with solder dots that aren't connected ground, and thus can't be fixed by moving the ground pin in place of the solder dot.

The solder dots indicate the two crossing wires are electrically connected (i.e., one net) and are not just crossing. If you couldn't easily distinguish between these two cases, debugging large designs would be a nightmare. When drawing new wires, the schematic editor will sometimes connect them electrically even if that's not what you wanted. So, if generates warning for all solder dots to try to force the designer to verify that the dots are intended.

Need to print black on white, how to invert color scheme? (from Myung-Chul Kim)

Inverting color scheme in timing diagram is straightforward. Click on Frames > Color Schemes > White in the menu. You can save as file by click on File > Save as Image. (Make sure you turn off desktop effects of Redhat Linux, if you're using them).

Inverting color scheme in schematic needs some procedures.

  1. Quit Cadence Tool
  2. Type the following command in the terminal
    echo "Opus.editorBackground: white" | xrdb -merge
  3. Re-run Cadence Tool and open your schematic.
  4. Your schematic should have a white background now.

To save as an image, press ALT+PrintScrn. If you want to get back to a black background,

  1. Quit Cadence Tool.
  2. Type the following command in the terminal
    echo "Opus.editorBackground: black" | xrdb -merge

MOSFET symbols.

How to use “integ” function (from Myung-Chul Kim).

This are steps for integrating some signal (current in our lab project) over a finite time interval.

  1. Draw your schematic and open Analog Design Environment.
  2. Set your Transient analysis.
  3. Outputs→To Be Plotted→Select on Schematic and choose your probing points (after that make sure the opt for To Be Saved is checked).
  4. Run simulation and a plot for probing points should show up.
  5. Click on a signal you want to integrate and click Tools→Calculator.
  6. Find and click “Integ” among available functions.
  7. You can specify integration intervals by typing in specific times in “Initial Value” and “Final Value”. E.g., if you want to integrate a signal from 2n to 3n, type in 2n for “Initial Value” and 3n for “Final Value”.
  8. You should find the interval first — from the input transition to 90% output transition.
  9. Click Apply and Eval will show the results.

Page maintained by Robert Dick.