Lecture Notes

Packet one — Digital system design in a nutshell Print version
Packet two — CMOS logic review Print version
Packet three — Two-level minimization Print version
Packet four — Heuristic two-level minimization Print version
Packet five — Review, Q&A, and scripting Print version
Packet six — Hierarchical design and transmission gate based design Print version
Packet seven — Technology mapping Print version
Packet eight — Multilevel minimization, timing Print version
Packet nine — Latches, from regular expressions to finite state machines Print version
Packet 10 — Arithmetic Print version
Packet 11 — Finite state machine optimization Print version
Packet 12 — Hardware design languages, introduction to VHDL Print version
Packet 13 — Asynchronous finite state machine synthesis Print version
Packet 14 — Introduction to testingPrint version

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