EECS 203 Mailing List
Decoder


Decoder

From: Hyerim Shin <hyerimshin2007_at_avoiding.spam>
Date: Sun Apr 13 2008 - 15:20:56 CDT

For my decoder, I have outputs of H,C,P,S,D with some combination of JKL.
When I drew the circuit diagram, I needed 6 two input AND gate, 1 three
input And gate, and 3 inverters.
Is there a method I can simplify this to four two input AND, One three input
And, three inverters as given in the lab handout? I am confused how to
simplifiy this because I cannot combine the outputs.
Thank you

Hyerim
Received on Sun Apr 13 15:20:56 2008

This archive was generated by hypermail 2.1.8 : Sat Aug 23 2008 - 21:08:11 CDT