EECS 303 Mailing List
Re: Lab 3 FSM


Re: Lab 3 FSM

From: Ben Schnur <b-schnur_at_avoiding.spam>
Date: Wed Nov 12 2008 - 17:07:41 EST

Tao,

Thanks so much for the clarifications!

That helps a lot.

On Wed, Nov 12, 2008 at 3:51 PM, Tao Zhao <x6a8d2@u.northwestern.edu> wrote:

> For the trap state, I think you don't need it. Only in the address driven
> one cycle, the W and addresses should be concerned. In other cycles, it does
> not matter at all what the W and the addresses are.
>
> For the setup/hold times, you need to consider them. That means, for
> example, only at the end of the address driven cycle, the addresses are
> valid. They are not valid at the beginning of that cycle.
>
>
> On Wed, Nov 12, 2008 at 3:00 PM, Ben Schnur <b-schnur@northwestern.edu>wrote:
>
>> Hello all,
>>
>> Does anyone know whether we need to include a trap state in our Mealy FSM?
>>
>> That is, can we assume there are no invalid input combinations?
>>
>> I cannot see how it is possible to reduce the number of inputs to 1
>> without assuming this.
>>
>> Also, in our timing diagram, do we need to worry about setup/hold
>> times for input values or
>> are we ignoring them since we are doing a digital simulation that
>> ignores delays?
>>
>> Any feedback is appreciated.
>>
>> Thanks,
>>
>> Ben
>>
>>
>

-- 
Ben Schnur
Northwestern University 2010
McCormick School of Engineering
Received on Wed Nov 12 16:07:41 2008

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