EECS 303 Mailing List
Re: Lab 3 FSM

Re: Lab 3 FSM

From: Robert Dick <dickrp_at_avoiding.spam>
Date: Thu Nov 13 2008 - 11:24:53 EST

Ben Schnur:
> Hello all,
> Does anyone know whether we need to include a trap state in our Mealy FSM?
> That is, can we assume there are no invalid input combinations?
> I cannot see how it is possible to reduce the number of inputs to 1
> without assuming this.
> Also, in our timing diagram, do we need to worry about setup/hold
> times for input values or
> are we ignoring them since we are doing a digital simulation that
> ignores delays?
> Any feedback is appreciated.

I did not need to use a trap state for Lab 3. Note that you cannot reduce the
entire system to one input. You can only break the system into a
combinational network with multiple inputs and one output, as well as a FSM
with one input.

Best Regards,

-Robert Dick-
Received on Thu Nov 13 10:24:53 2008

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