EECS 303 Mailing List
Re: Lab 3 timing

Re: Lab 3 timing

From: Robert Dick <dickrp_at_avoiding.spam>
Date: Thu Nov 13 2008 - 00:24:30 EST

> I was pondering the lab handout's description of the timing of the FSM
> and ran into the following issue:
> If we don't raise H (data hold) a cycle before the data is driven (but
> rather, raise it when we start to drive the data) , it might be read
> as zero at the start of driving the data (not stable yet) causing the
> data to be driven for only one cycle.
> However, if we raise it a cycle before the data starts to be driven,
> the address values are not yet valid because the driving of those has
> not yet finished. That implies that we would not be able to use any
> address bits to determine next state / output when we raise H.
> Am I misunderstanding something here? It seems as if we need a cycle
> between the address-driving cycle and the first data-driving cycle in
> order for H to be (a) computed using address bits and (b) stable in
> time to be read as high when the data-driving cycle starts.
> Of course, the handout says that there is no such intermediate cycle.
> Any thoughts?

Does this help?

"However, regardless of the value on H during the address cycle, the data bus
will be driven for at least one cycle."

-Robert Dick-
Received on Wed Nov 12 23:24:30 2008

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