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VHDL

From: Hyerim Shin <hyerimshin2007_at_avoiding.spam>
Date: Wed Dec 10 2008 - 16:16:01 EST

Could you help me how to interpret this code?

clock_gen: process (clk) is

begin

if clk = '0' then

clk <= '1' after T_pw, '0' after 2*T_pw;

endif;

end process clock_gen;
Received on Wed Dec 10 15:16:01 2008

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