EECS 303 Mailing List
Re: VHDL


Re: VHDL

From: Mykell Miller <mykell.shih_at_avoiding.spam>
Date: Wed Dec 10 2008 - 16:23:15 EST

This would create something like this:

       ____
______| |________

It would create one pulse with period 2*T_pw.

On Wed, Dec 10, 2008 at 3:16 PM, Hyerim Shin <
hyerimshin2007@u.northwestern.edu> wrote:

> Could you help me how to interpret this code?
>
>
> clock_gen: process (clk) is
>
> begin
>
> if clk = '0' then
>
> clk <= '1' after T_pw, '0' after 2*T_pw;
>
> endif;
>
> end process clock_gen;
>
>

-- 
Mykell Miller
Received on Wed Dec 10 15:23:15 2008

This archive was generated by hypermail 2.1.8 : Tue Jan 06 2009 - 18:55:01 EST