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Tech. Mapping non-tree DAGs

Tech. Mapping non-tree DAGs

From: Ben Schnur <b-schnur_at_avoiding.spam>
Date: Wed Dec 10 2008 - 22:23:21 EST

Hi Professor.

Could you briefly describe how you would go about "gluing" a DAG back
together after splitting it to make it a tree and mapping gates?

For example, how would you do so for the circuit on slides 31-59 of lecture

(I think I see how you split it - you put an inverter in place of a NAND2,
so are we to assume you would replace any gate whose input you "chop" with
something that would be equivalent if the "chopped" input were set to 1?)



On Wed, Dec 10, 2008 at 6:31 PM, Robert Dick <>wrote:

> Anitha Mohan:
> > Dear Professor,
> >
> > Do we have to cover sequential testing and design/ synthesis for
> > testability or do we have to cover only combinational testing for the
> > final?
> Sequential testing should be understood to the following extent. You
> should
> understand the implications of unrolling a sequential circuit in time in
> order to use combinational test generation for the sequential circuit. The
> lecture notes have a couple of slides on this that should make the concept
> clear (see Iterative array expansion). If you have any questions on that,
> please ask. The idea is to copy the circuit for as many cycles as the
> longest path in the finite state machine and feed the next-state variables
> directly into the state variable lines of the subsequent copy. Then
> combinational test generation can be used on the unrolled circuit to
> generate
> a test for the sequential circuit. I will not ask questions directly on
> sequential test generation. However, understanding the concept will help
> you
> understand what finite state machines are, which will help you in other
> areas
> of life.
> We did not cover scan-flops, 9-value logic, or design for testability and I
> do
> not expect you to learn those from the lecture notes.
> -Robert Dick-
Received on Wed Dec 10 21:23:21 2008

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