Articles
Note: These articles are copyrighted so I have restricted access to
students in the class. Email me if you need access.
- S. Kim, R. P. Dick, and R. Joseph, “Power
Deregulation: Eliminating Off-Chip Voltage Regulation Circuitry From Embedded
Systems,” to appear in Proc. Int. Conf. Hardware/Software
Codesign and System Synthesis, Sep. 2007. Notes: Technique to eliminate
power regulation hardware from embedded chip multiprocessors.
- A. Mallik, B. Lin, G. Memik, P. Dinda, and R. P. Dick, “User-Driven Frequency
Scaling,” in IEEE Computer Architecture Letters, vol. 5,
no. 2, Dec. 2006. Notes: Describes a new technique to reduce laptop power
consumption by 22% by directly considering user satisfaction.
- C. Zhu, Z. P. Gu, L. Shang, R. P. Dick, and R. Knobel, “Towards an Ultra-Low-Power
Architecture Using Single-Electron Tunneling Transistors,” in
Proc. Design Automation Conf., pp. 312–317, Jun. 2007. Notes:
One of 15 best paper award nominees out of 713 submitted papers. First
work to evaluate the architectural implications of using single-electron
tunneling transistors for numerous embedded and general-purpose
processors.
- L. Bai, L. Yang, and R. P. Dick, “Automated Compile-Time and Run-Time
Techniques to Increase Usable Memory in MMU-Less Embedded Systems,”
in Proc. Int. Conf. Compilers, Architecture & Synthesis for Embedded
Systems, pp. 125–135, Oct. 2006. Notes: Compiler-assisted on-line
data compression technique permits substantial increases in usable memory on
MMU-less embedded systems, such as sensor network nodes.
- R. P. Dick, L. Shang, and N. K. Jha, “Power-Aware Architectural Synthesis,”
in The VLSI Handbook, W.-K. Chen, Ed. CRC Press, 2006. Notes: Survey
of recent progress in power-aware and temperature-aware high-level and
system-level synthesis.
- Chee-Yee Chong and Srikanta Kumar, Sensor Networks: Evolution, Opportunity, and
Challenges,” in Proc. IEEE, vol. 91, no. 8, Aug. 2003.
- K. Meng, F. Huebbers, R. Joseph, and Y. Ismail, “Modeling and Characterizing Power
Variability in Multicore Architectures,”, in Proc. Int. Symp. on
Performance Analysis of Systems & Software, 2007.
- L. Yang, R. P. Dick, H. Lekatsas, and S. Chakradhar, “On-Line Memory Compression for
Embedded Systems,” to appear in ACM Trans. Embedded Computing
Systems. Notes: NEC used this technology in their cellphones in June
2007. Operating system technique to double usable memory in embedded
systems without changing applications, or hardware, and with little or no
performance or power penalty.
- Haris Lekatsas, Jörg Henkel, and Wayne Wolf, “Code compression for low
power embedded system design,” in Proc. Design Automation
Conf., pp. 294–299, Jun. 2000.
- R. P. Dick, L. Shang, and N. K. Jha, “Power-Aware Architectural
Synthesis,” in The VLSI Handbook, W.-K. Chen, Ed. CRC Press,
2006. Notes: Survey of recent progress in power-aware and temperature-aware
high-level and system-level synthesis.
- Wayne Wolf, “Embedded
Computing Systems and Hardware/Software Co-Design,” The VLSI
Handbook, 2006.
- Shiv Prakash and Alice C. Parker, “Synthesis of Application-Specific
Multiprocessor Architectures,” Proc. Design Automation
Conf., Jun. 1991.
- S. D. Johnson, “Formal Methods
in Embedded Design,” IEEE Computer, vol. 36, no. 11,
Nov. 2003.
- L. Yang, R. P. Dick, H. Lekatsas, and S. Chakradhar, “On-Line Memory Compression for
Embedded Systems,” to appear in ACM Trans. Embedded Computing
Systems. Notes: NEC used this technology in their cellphones in June
2007. Operating system technique to double usable memory in embedded
systems without changing applications, or hardware, and with little or no
performance or power penalty.
- Z. P. Gu, J. Wang, R. P. Dick, and H. Zhou, “Unified Incremental Physical-Level and
High-Level Synthesis,” to appear in IEEE Trans. on Computer-Aided
Design of Integrated Circuits and Systems. Notes: Rapid, high-quality
floorplanning within behavioral synthesis, merging the behavioral and physical
design levels and permitting interconnect power optimization for large
designs.
- Z. P. Gu, Y. Yang, J. Wang, R. P. Dick, and L. Shang, “TAPHS: Thermal-Aware Unified
Physical-Level and High-Level Synthesis,” Proc. Asia & South Pacific Design
Automation Conf., Jan. 2006. Notes: One of eight best paper award
nominees out of 432 submitted papers. Efficient and high-quality unified
thermal analysis, floorplanning, and high-level synthesis algorithm.
- C. Zhu, Z. P. Gu, R. P. Dick, and L. Shang, “Reliable Multiprocessor System-On-Chip
Synthesis,” to appear in Proc. Int. Conf. Hardware/Software
Codesign and System Synthesis, Sep. 2007. Notes: Temperature-aware
reliability optimization techniques for use in multiprocessor system-on-chip
synthesis.
- Y. Liu, R. P. Dick, L. Shang, and H. Yang, “Accurate Temperature-Dependent
Integrated Circuit Leakage Power Estimation is Easy,” in
Proc. Conf. on Design, Automation, and Test in Europe,
pp. 204–209, March 2007. Notes: First paper to clearly indicate thermal
modeling conditions necessary and sufficient for accurate leakage estimation,
resulting in reduced modeling complexity and orders of magnitude speedup
compared with previous practice.
- S. Jevtic, M. Kotowsky, R. P. Dick, P. A. Dinda, and C. Dowding, “Lucid Dreaming: Reliable Analog
Event Detection for Energy-Constrained Applications,” in
Proc. Int. Symp. Information Processing in Sensor Networks,
pp. 350–359, Apr. 2007. Notes: Ultra-low-power event detection sensor
interface technology permits 250× reduction in power consumption for
event-driven applications such as structural integrity monitoring of buildings
and bridges.
- R. P. Dick, Multiobjective
Synthesis of Low-Power Real-Time Distributed Embedded Systems,
Ph.D. Dissertation, Dept. of Electrical Engineering, Princeton University,
Nov. 2002.
- Stephen Edwards, Luciano Lavagno, Edward A. Lee, and Alberto
Sangiovanni-Vincentelli, “Design of embedded
systems: formal models, validation, and synthesis,”
Proc. IEEE, Mar. 1997.
References
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